This invention relates to frequency synthesizers in general, and more particularly to fractional-N-frequency synthesizers for producing variable modulated output frequency f.sub.out.
Frequency synthesizers generally comprise phase lock loop (PLL) circuits which provides many frequency outputs from a single reference frequency. In a PLL circuit, various output frequencies f.sub.out may be produced by varying a loop divisor K. The loop divisor K is programmed into a programmable divider circuit in order to set the desired output frequency f.sub.out. The output of the programmable divider is applied to a phase detector which operates in a conventional manner comparing the phase of the divided output signal with a reference frequency f.sub.ref from a reference oscillator. The output of the VCO is locked to the desired frequency when no phase error exists between the phase detector inputs. Accordingly, the output frequency of the synthesizer f.sub.out =K*f.sub.ref.
Fractional-N-synthesizers may be used to increase the frequency resolution of the PLL circuit as well as maintaining a fast frequency lock time. In fractional-N synthesizers, the output frequency f.sub.out is related to a reference frequency source by the relationship f.sub.out =(M.F.).times.f.sub.ref. Where M.F is equal to the divisor value K. In the fractional synthesizer, (M.F) is produced by a fractional loop divider and consists of an integer part M and a fractional part F. The fractional part F is equal to N/D where N is a fractional numerator and D is a fractional denominator. N and D comprise integer numbers. When f.sub.out is an integer multiple of the f.sub.ref, the fractional part F as well as N are equal to zero. On the other hand, when f.sub.out is not an integer multiple of the f.sub.ref, the M.F is a real value for all the non-zero values of N. Because a digital divider operates with integer values, fractional division is simulated by switching between different integer values of divisors such that the average divisor value is equal to the loop divisor K. However, this switching of the divisors results in spurious sidebands. The goal in designing a synthesizer is to keep the amplitudes of these sub-harmonic spurs below some acceptable limit.
In a fractional-N synthesizer disclosed by Martin in U.S. Pat. No. 4,816,774, the spurious side bands are improved by providing dual accumulator compensation means. In Martin's fractional N-synthesizer, the compensating means reduce the generated spurs for all non-zero values of N by integrating the fundamental. An offset value may be selectively introduced in the accumulators in order to produce a wave from having an acceptable spurious content. However, Martin's fractional synthesizer does not provide any compensation, when N is equal to zero because the spurious signals are generated only when the programmable divider performs a fractional division. No spur is generated when the programmable divider performs an integer division.
In some applications, such as in transmitter local oscillator applications, it may become necessary to modulate the output frequency f.sub.out with a modulating signal which may contain voice or data messages. In these applications the divider value of the programmable divider as well as the VCO are modulated with the modulating signal. One such method of modulation is disclosed in a pending U.S. patent application Ser. No. 07/499,102 filed on 3/26/1990, now U.S. Pat. No. 4,994,768, and assigned to the assignee of the present application. In this method, the programmable divider is modulated by varying the loop divisor K in accordance with the digital representation of the modulating signal. In cases where f.sub.out is an integer multiple of the f.sub.ref (i.e. N=0) application of the modulating signal may provide an instantaneous non-zero value for N. Therefore, the fractional N synthesizer of the prior art may not compensate for the generated spurs due to instantaneous non-zero value of N which is caused by the application of the modulating signal since compensation only occurs for non-zero values of N.